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modl_audio_synthesis

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Basics

Audio Sample Rate == 65536Hz Channels == 2 Bits per sample == 16bits 65536values (signed/unsigned is irrelevant) Sub-sample accuracy. 0. Max Length at 32 bits : 18h12m16s Or use 64 bits to get 1/65536 sample sub sampling and huge bump (2^32) in longevity.

256 bytes of output is 64 samples = ~1ms.

Functions

add, mul, sub, div shl, shr, asl, asr cl0, cl1 bop (and, or, xor, nand, nor etc)

Lower level machine is 2 interoperable alus capable of handling cordic operations, 2 way simd etc.

Networks are made of modules with inputs, outputs and some function in-between - temporary variables are invisible from the outside.

Execution order is via a topological sort.

I want to support loops (Cyclic Graphs) with the understanding that for every loop there is a cycle delay - that is the output of a module must be cached at multiple T minus deltas to support cyclic graphs.

It is physically impossible to have a 0 cycle feedback loop. Even analogue can't do this BUT analogue is pumping electrons maybe 10mm at 99% light speed.

At 3*10^8 metres per second (3*10^11 millimetres/second) traveling 10 millimetres is only going to to take 3*10^-10 seconds - a LONG way from 65536Hz (and that's why analogue sounds better! It's like oversampling a million times - any creature with much better hearing than a human will immediately tell the difference).

modl_audio_synthesis.txt · Last modified: 2018/02/01 05:50 by xylene